The present invention relates, in general, to interfacing Input/Output (I/O) interfaces with an array of multicore processor resources that are connected in a tiled architecture. In particular, the present invention relates to providing a dynamic software-controlled hardware interface between the I/O interfaces and the array of multicore processor resources.
I/O interfaces are hardware circuits that are designed to process, initialize and move data in a semiconductor chip. Examples of I/O interfaces include a 10 Gbe, a PCIe, Gbe I/Os, and the like. The hardware circuitry of an I/O interface depends on its usage model and application. For example, some applications require transfer of the data prior to processing it, while other applications require processing of the data prior to its transfer. The I/O interfaces are connected to the processor resources. The processor resources processes the data received from the I/O interfaces. The I/O interfaces are generally connected to the processor resources by hardwired connections that are designed based on a predefined addressing scheme. Examples of predefined addressing schemes include a memory-mapped addressing scheme and an I/O-mapped addressing scheme. The I/O interface connections do not facilitate the flexibility of dynamically connecting the I/O interfaces with the processor resources.
The hardware circuitry is designed by using common buses, such that a particular I/O interface can only communicate with its corresponding processor resource. This adds to the complexity of the circuit, particularly if the number of I/O interfaces and/or processor resources is large. Consequently, the circuitry requires additional chip area, and each processor resource is rigidly pre-assigned to an I/O resource. Moreover, the combination of a particular processor resource and its corresponding I/O interface is also fixed.
Alternatively, tri-state bus architecture can be used in the hardware circuitry. The tri-state bus architecture allows a limited number of processor resources to be dynamically linked to the I/O interfaces. The limit of the number of processor resources linked to I/O interfaces is based on the electrical characteristics, such as current requirements, acceptable transfer delays, and the like. Additionally, the tri-state bus architecture has to ensure no contention on tri-state buses during every scan shift operation in Automatic Test Pattern Generating Concerns (ATAG). ATAG is used to distinguish between the correct circuit behavior and the faulty circuit behaviors caused by any fault in the design or performance of the circuit.
In light of the foregoing discussion, there is a need for a method and system for dynamically managing I/O interfaces with an array of multicore processor resources. Such a method and system should provide a dynamically controlled hardware circuit to connect I/O interfaces to the array of multicore processor resources that use the chip area efficiently. This would eliminate any predetermined binding of a particular processor resource with a corresponding I/O interface. Further, such a system should be scalable, so that one or more of the processor resources can be connected to an I/O interface, depending on its characteristics. Furthermore, such a system should facilitate the assignment of processor resources to the I/O interfaces in any desired combination.